1. Field of the Invention
Example embodiments of the present invention relate generally to an interposer and a stacked chip package having an interposer and, more particularly, to an interposer that may have a plurality of regularly formed lands, and to a stacked chip package that may implement such an interposer.
2. Description of the Related Art
Package stacking technologies may involve stacking multiple semiconductor chips to achieve a high degree of integration in semiconductor devices. Due to conditions such as the sizes of the semiconductor chips to be stacked and/or the number or arrangement of chip pads thereof (for example), the chip pads of an upper semiconductor chip may be reconfigured to be stacked on a lower semiconductor chip.
An interposer may be implemented to reconfigure the chip pads of the upper semiconductor chip. Although the conventional interposer is generally thought to provide acceptable performance, it is not with shortcomings. For example, according to conventional wisdom, the interposer may be separately fabricated (and customized) according to assembly conditions of semiconductor chips and a package substrate of a particular stacked chip package.
FIGS. 1A and 1B illustrate a stacked chip package that implement a conventional interposer.
As shown in FIGS. 1A and 1B, the conventional stacked chip package 1 may include a package substrate 2. A first semiconductor chip 3 may be mounted on the package substrate 2. An interposer 5 may be stacked on the first semiconductor chip 3. A second semiconductor chip 4 may be stacked on the interposer 5.
In the stacked chip package 1, an adhesive 12 may provide bonds between the package substrate 2 and first semiconductor chip 3, between the first semiconductor chip 3 and interposer 5, and between the interposer 5 and second semiconductor chip 4.
Substrate pads 6 may be provided on the upper surface of the package substrate 2. The substrate pads 6 may be electrically connected to corresponding first chip pads 7 provided on the upper surface of the first semiconductor chip 3 through bonding wires 11.
Second chip pads 8 may be provided on the upper surface of the second semiconductor chip 4. The second chip pads 8 may be electrically connected to corresponding substrate pads 6 through a first bonding pad 9a, a second bonding pad 9b, and connection wires 10 that may be provided on the upper surface of the interposer 5.
By virtue of the interposer 5, a second chip pad 8 need not be directly connected to a corresponding substrate pad 6 through a lengthy bonding wire. Instead, the second bonding pad 9b may be connected to an associated second chip pad 8 through a bonding wire 11. The second bonding pad 9b may be electrically connected to the first bonding pad 9a through the connection wire 10. The connection wire 10 may have a predetermined pattern on the upper surface of the interposer 5. The first bonding pad 9a may be connected to a corresponding substrate pad 6 through another bonding wire 11.
The first bonding pads 9a, the second bonding pads 9b and the connection wires 10, which may be implemented to reconfigure the second chip pads 8, may be custom fabricated according to fabrication conditions of the stacked chip package 1, such as the number and arrangement of the substrate pads 6, the number and arrangement of the chip pads 7 and 8, and/or the sizes of the semiconductor chips 3 and 4, for example.
That is, to interconnect the second bonding pads 9b and the second chip pads 8, the second bonding pads 9b may be provided corresponding in number and position to the second chip pads 8. Similarly, the first bonding pads 9a may be provided corresponding to the substrate pads 6.
The connection wires 10, each of which may interconnect a first bonding pad 9a and an associated second bonding pad 9b, may have predetermined patterns corresponding to the arrangement of the first bonding pads 9a and the second bonding pads 9b. 
If fabrication conditions of the stacked chip package 1 are altered, for example, an increase in number and/or a change in position of the first chip pads 7 and the second chip pads 8 or a change in size of the second semiconductor chip 4 to be stacked, then a new (and customized) interposer may be fabricated according to the changed fabrication conditions.
The custom fabrication of interposers according to fabrication conditions of individual stacked chip packages may increase overall package manufacturing costs and/or adds extra steps to an overall package manufacturing process.